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Casio FX-870P - hardware

The microprocessor

On this page only information specific to the FX-870P is shown. See the PB-1000 hardware page for more general information about the microprocessor and the bus waveforms.

Decoded address ranges for the chip select signals

CS0: &H00C00..&H0FFFF and &H20000..&H2FFFF, ROM 128kB
CS1: &H34000..&H37FFF, unused
CS2: &H30000..&H30001, unused
CS3: &H38000..&H3FFFF, peripheral port
CS4: &H32000..&H33FFF, unused
CS5: &H31000..&H31FFF, unused
CS6: &H10000..&H1FFFF, gate array (RAM address space)
CS7: &H30000..&H30007, gate array (registers)

Function of individual bits of the 8-bit port

P7..P6 drive the piezo-buzzer
P5 is the printer port BUSY input
P4 selects the language version, connected either through the PAD3 jumper to +5V (Japanese VX-4) or through the PAD4 jumper to GND (English FX-870P)
P3 is the printer port STROBE output
P2 is the printer port INIT output
P1 is not connected
P0 receives high level from the S8054ALR battery monitor chip when valid supply voltage is present

The clock signals Ø1 and Ø2 are distributed to the peripheral devices through a loading coil.

The power supply circuit

power supply circuit diagram

Unlike the PB-1000 and PB-2000C, the FX-870P uses the negative supply voltage rail as ground (GND).

The gate array

gate array pin functions

Pin functions

PinSymbol Function
1Poff controls the Poff input of the voltage converter chip SCI7661
20VDD1 receives low level from the microprocessor pin 33 when the power is on
23OPT1 selects the RAM configuration, connected either through the PAD1 jumper to +5V (8kB RAM soldered on the board) or through the PAD2 jumper to GND (32 kB RAM soldered on the board)
24WR bus write strobe signal, active low
25OE data strobe control signal
bi-phase clock signal from the microprocessor
29INT1 interrupt request output, active low
30CS7 chip enable input for the gate array registers, receives low level from the microprocessor for address range &H30000..&H30007
31CS6 chip enable input for the RAM address space, receives low level from the microprocessor for address range &H10000..&H1FFFF
32..39IO7..IO0 bi-directional data bus
40..41A0, A1 address bus inputs
43..47A2, A12..A15 address bus inputs
48..50XA12..XA14 address bus outputs for the RAM, the same state as A12..A14 when the OPT1 input is high, or after subtracting an offset of &H3000 from the address sent by the microprocessor when the OPT1 input is low
This address translation is redundant, the system would work just as well with the RAM connected directly to the microprocessor address bus.
55TXD serial port transmit data output
serial port control signals
59RXD serial port receive data input
serial port status signals
63XCS0 chip enable output for the RAM soldered on the board, decoded address range &H11000..&H12FFF when the OPT1 input is high, or &H10000..&H17FFF when the OPT1 input is low
64XCS1 chip enable output for the RAM expansion module, decoded address range &H13000..&H1AFFF when the OPT1 input is high, or &H18000..&H1FFFF when the OPT1 input is low

Register addresses

A2 A1 A0 Access Function
010 Read serial port receive data register
Write serial port transmit data register
011 Read bit 0 - set when the transmitter is ready for data to be sent
bit 1 - flag of a received byte, cleared after reading the data register 010
bit 2
bit 3 - set by a parity error
bit 4 - set by an overrun error
bit 5 - set by a framing error
Write bit 0
bit 1
bit 2 - set when 8 data bits, cleared when 7 data bits
bit 3
bit 4 - set turns the parity control on
bit 5 - set when parity even, cleared when parity odd
bit 6 - set for this function
bit 7 - set when 2 stop bits, cleared when 1 stop bit
100 Read/Write bit 0..2 - baud rate
bit 3
bit 4 - set when MT, cleared when RS232C
bit 5
bit 6 - receiver enable
bit 7 - transmitter enable
101 Read/Write bit 4 - inversion of the loaded MT signal
110 Read bit 0 - set on valid carrier tone from the tape
bit 2 - state of the CTS input (inverted)
bit 3 - state of the DSR input (inverted)
bit 4 - state of the DCD input (inverted)
bit 7 - state of the OPT1 input
111 Read/Write  

Baud rate selects



The LCD and keyboard connectors

01 - GND
02 - +5V        
03 - VLCD
04 - ON
05 - Ø1
06 - Ø2
07 - OP
08 - CE1
09 - CE2
10 - VDD2
11 - D0
12 - D1
13 - D2
14 - D3
15 - GND
01 - GND
02 - KI12
03 - KI11
04 - KI10
05 - KI9
06 - KI8
07 - KI7
08 - KI6
09 - KI5
10 - KI4
11 - KI3
12 - KO1
13 - KO2
14 - KO3
15 - KO4
16 - KO5
17 - KO6
18 - KO7
19 - KO8
20 - KO9

The keyboard layout

The columns of the keyboard matrix are driven from the 12-bit KO output port, controlled by the IA register. A pressed key makes contact between selected column and row. The rows are sensed by the 12-bit KI input port, accessible through the KY register.

keyboard layout

Mapping of the KY register bits to the keyboard rows:

KY register bit mapping

The RAM expansion module connector

RAM expansion module connector

The peripheral port connector

peripheral port connector