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Casio FX-8000G - hardware

The μPD1007 microprocessor

microprocessor uPD1007

Pin functions

PinSymbol Function
IO7..IO0 bi-directional data bus
6,7OSC1,OSC2 ceramic resonator 910kHz, OSC2 is the output from the inverting oscillator amplifier
8..11A12..A15 address bus
12..14CS1..CS3 Chip select signals for three additional memory banks, active low.
CS1: FA-80 interface
CS2,CS3: single bit output port CNTL in the gate array uPD65005G-045
15EN1 Single bit output port, low level turns the system power on.
16EN2 Single bit output port, drives the INT0 interrupt input allowing software triggered interrupts.
17SW Power switch input, connected either to VDD1 (power on) or to GND (power off).
LCD controller bus, similar as in the Casio FX-700P,
all signals use negative logic,
pins CE2 and CE3 are not connected in the FX-8000G
26INT0 interrupt input, driven from pin EN2
27INT1 interrupt input, receives low level pulses from pin 27 of the HD44352 LCD controller chip
28INT2 interrupt input, used by the FA-80 interface
33GND positive supply voltage
35VDD1 permanent negative supply voltage
36VDD2 switched negative supply voltage
KI0..KI7 keyboard matrix input port, can be accessed through the KI register
47..58KO1..KO12 keyboard matrix output port, controlled by the KO register
59OE bus read signal, active low
A0..A11 address bus
73WE bus write signal, active low
74FE memory chip select signal, active low

The bus waveforms

Reading from the memory

A084: A9 02    LD R2,(IY)+

bus waveforms, reading from the memory

Writing to the memory

A086: 89 02    ST +(IY),R2

bus waveforms, writing to the memory

The keyboard

The columns of the keyboard matrix are driven from the 12-bit output port KO. A pressed key makes contact between selected column and row. The rows are sensed by the 8-bit input port KI.

keyboard layout

The gate array μPD65005G-045

gate array uPD65005G-045 circuit diagram

The peripheral port connector

peripheral port connector